The AnastASICA project set out to create a new design infrastructure that would enable small and medium‑sized enterprises to develop and market application‑specific integrated circuits (ASICs) with significantly lower risk and cost than current practices. Traditional ASIC development relies heavily on building a system from scratch, which discourages reuse of existing intellectual property (IP). AnastASICA addressed this by combining reusable IP blocks, innovative design‑migration techniques, and rapid, efficient system‑level modelling and optimisation. The consortium estimated that the new methodology could cut development effort by up to 50 % and improve product quality by up to 30 % compared with conventional approaches.

A core technical achievement was the construction of a fully automated design flow that spans from system specification down to transistor‑level layout. The flow incorporates parametric system‑level models, circuit exploration and optimisation, topology reuse through IP libraries, and a template‑based layout generator. The generator uses a layout API that accepts array arrangements and produces silicon‑ready layouts in a fraction of the time required by traditional hand‑crafted methods. In a representative study, the inner optimisation loop—optimising layout‑level estimates derived from templates—completed in roughly five seconds, while the outer loop, which feeds the template estimates into a parametric ADC model to predict pipeline performance, finished in under one minute. Compared with a full Spice simulation that would normally take a working day, this approach delivers a speedup of about 500 ×, enabling designers to iterate rapidly and obtain quantified performance predictions early in the design cycle.

The project also demonstrated the practical value of the new flow by implementing several IP blocks for high‑frequency wireless communication and signal conversion, targeting automotive sensor‑signal acquisition and data‑transfer applications. These IPs were validated through a combination of schematic porting tools, SystemC‑AMS simulations, and physical layout verification. The resulting ASIC prototypes exhibited the expected signal‑to‑noise ratios and linearity metrics, confirming that the reuse‑centric methodology does not compromise performance. Moreover, the use of JSON as an interchange format between WiCkeD, the layout generators, and the SystemC‑AMS simulation environment ensured seamless data flow across the entire design chain.

Collaboration within AnastASICA involved a consortium of research institutes and industry partners. The Technical University of Kaiserslautern (TUKL‑CPS), MunEDA, IIS/EAS, and IMST led the development of the design‑flow tools and the parametric models. These partners worked closely with the automotive‑sector stakeholders to tailor the IP blocks for real‑world use cases. The project was funded under a European Union programme, with the consortium receiving support that allowed for the extension of the project timeline to accommodate unforeseen challenges such as the COVID‑19 pandemic, the global chip shortage, and delays in hardware characterization equipment. Despite these disruptions, all ten planned milestones were achieved, and the consortium published a series of papers and presented findings at international conferences, underscoring the relevance and impact of the developed methods.