Systolic Arrays (SA) provide efficient mechanisms for processing a variety of data, from image and video processing to neural networks. The scalar core provides the control and orchestration of the SA, and the L2 scratchpad provides the streaming memory interface to the SA to enable sustained high performance. To support different kinds of applications, MEEP proposes a common SA Shell template for all of them. This template fixes the interfaces with the scalar processor, and memory, but the final internal structure of the computational block will depend on the nature of the application to be executed.