This funding call, titled "Chiplet for Defence Application", invites proposals that explore a new paradigm in defence electronics by leveraging the chiplet approach. The concept of a chiplet involves designing integrated circuit blocks that are pre‐qualified and can be interconnected with other chiplets to form complex systems. This approach is set to overcome the limitations of conventional components such as FPGAs, which offer generic, limited performance solutions, and ASICs, which, although high-performing, come with very high development costs. The call aims to harness the advantages of chiplet architecture – notably, reduced development and manufacturing costs through the reuse of existing building blocks and higher manufacturing yields compared to large monolithic dies. An additional benefit is the potential to incorporate off-the-shelf chiplets, thus mitigating supply chain vulnerabilities while offering the flexibility to scale the performance and functionality of a System-in-Package (SiP) design by simply adding or removing chiplets.

In this call, applicants are expected to carry out a comprehensive analysis of the current state-of-the-art in chiplet-based architectures and to demonstrate how these can be applied to various defence applications such as radar systems, electronic warfare systems, communication systems, munition applications, and signal processing applications. The proposal should include a thorough evaluation of available technologies – including chiplets made in different materials like GaN, GaAs, and Si – and discuss how heterogeneous integration (2.5D or 3D) can be exploited using EU-based advanced packaging facilities. Particular emphasis is placed on ensuring that the developed solution is not only cost efficient, even in low volume production scenarios, but also resilient with respect to supply chain dependencies and adaptable to harsh operational environments.

Applicants are required to undertake a series of mandatory tasks: generating knowledge by reviewing existing chiplet applications and analysing their performance benefits; integrating this knowledge to define electronic functions that can be implemented using the chiplet approach; and conducting feasibility studies to identify which off-the-shelf components can be used and which chiplets need to be developed. In addition, the proposals must outline detailed technical specifications, interface solutions between chiplets, and risk reduction strategies, including partial testing regimes. The design should also address cybersecurity challenges and comply with relevant regulatory standards such as REACH and ROHS. Furthermore, the call encourages exploring the scalability of the proposed architecture, ensuring that functionalities can be adjusted by modifying the number of chiplets in the system. Synergies with ongoing projects in advanced packaging and semiconductor technologies, such as those under Chips JU, should be clearly substantiated.

The expected impact of the call is significant. It aims to develop a common hardware library of chiplets that could serve as foundational building blocks for next-generation defence systems, thereby enhancing the competitive advantage of the European Defence Technological and Industrial Base (EDTIB). By fostering innovation in chiplet technology and promoting the use of EU-based technologies, the call also seeks to reduce dependency on external suppliers and increase the resilience and adaptability of military applications.

Opening: 18-02-2025
Deadline(s): 16-10-2025