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Description
This Research and Innovation Action (RIA) aims to strengthen international collaboration in semiconductor research between Europe and key strategic partner countries through low-TRL research and innovation. The call focuses on building partnerships with countries covered by EU Digital Partnerships and Trade and Technology Council (TTC) cooperation, particularly India, Singapore and Taiwan, to develop innovative semiconductor technologies while strengthening supply chain resilience, technological sovereignty and mutually beneficial research cooperation. The initiative targets areas where partner countries provide complementary expertise, including advanced packaging, heterogeneous integration and photonic chip technologies.
Funding Amount
Maximum EU budget for the topic
- EUR 5 million
Expected EU contribution per project
- EUR 2–2.5 million, although proposals requesting different amounts may also be submitted where appropriately justified. The call is funded through EU funding only (no co-financing by Chips JU Participating States).
Submission Deadlines
- Call launch: 7 July 2026
- Submission deadline (Full Proposal): 16 September 2026, 17:00 Brussels time
This is a one-stage call.
Eligible Types of Businesses
The call is open to organisations eligible under Horizon Europe and the Chips Joint Undertaking rules, including:
- SMEs
- Large enterprises
- Semiconductor manufacturers
- Universities
- Research institutes
- Research and Technology Organisations (RTOs)
- Design houses
- Materials suppliers
- Equipment manufacturers
- Packaging and integration companies
- Other eligible legal entities
Projects should bring together multidisciplinary expertise across the semiconductor value chain. In addition, consortia must collaborate with organisations from the targeted partner countries (India, Singapore and Taiwan), which participate as associated partners without EU funding.
Eligible Countries
Participation is limited to legal entities established in:
- EU Member States;
- EEA countries (Iceland, Liechtenstein and Norway);
- Horizon Europe Associated Countries;
- OECD countries;
- Mercosur countries;
- India;
- Singapore;
- Taiwan.
Additional security provisions apply to protect the strategic interests of the European Union. Entities controlled by non-eligible countries may be subject to restrictions, and entities directly or indirectly controlled by China cannot fulfil the required security guarantees under this topic.
Submission Conditions
- Research and Innovation Action (RIA).
- One-stage submission process.
- EU funding only (no co-financing by Chips JU Participating States).
- Maximum EU contribution to a single partner is limited to 30% of the total EU funding.
- Maximum consortium size: 20 partners.
- Consortia must include concrete collaboration with organisations from the targeted partner countries, participating as associated partners.
- Proposals are subject to the standard Chips JU/Horizon Europe admissibility, eligibility and evaluation rules, together with additional security provisions concerning international participation.
Target TRL
The topic explicitly targets early-stage research. Projects should address research with high innovation potential that reaches TRL 4, focusing on semiconductor design, fabrication processes and packaging technologies that have not yet been demonstrated at higher maturity levels.
Expected Outcome
Projects are expected to deliver:
- strengthened research collaboration between European organisations and Digital Partnership/TTC countries;
- innovative design and integration concepts for neuromorphic computing systems with very low energy consumption and embedded intelligence;
- new semiconductor manufacturing technologies supporting long-term improvements in device performance, miniaturisation, cost and environmental sustainability;
- advanced packaging solutions enabling heterogeneous integration of multiple functions and materials for communication, sensing, actuation and power management applications;
- stronger international semiconductor research networks supporting resilient and diversified semiconductor value chains.
Scope
Projects should undertake collaborative research with organisations from eligible Digital Partnership and TTC countries, addressing one or more of the following areas:
- research on semiconductor technologies with the potential to reach TRL 4, particularly in chip design, fabrication processes and packaging;
- development of innovative materials, physical concepts and device architectures based on neuromorphic computing or advanced integration technologies;
- alternative semiconductor manufacturing processes for front-end and back-end production supporting heterogeneous integration;
- advanced packaging technologies enabling heterogeneous integration of multiple materials and functions;
- innovative concepts for low-energy neuromorphic computing systems supporting connectivity, embedded intelligence and mobile applications;
- multidisciplinary research spanning the semiconductor value chain, including materials, manufacturing processes, equipment, metrology, back-end processing, packaging, integration and testing.
Consortia must demonstrate concrete cooperation with organisations from the targeted partner countries, which may participate as associated partners without EU funding. Applicants should quantify the expected technical improvements and key performance indicators of the proposed approaches.
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